Field of the Invention
The present invention relates to a C MOS IC with novel interconnection means between circuit blocks and cells.
As integrated circuits continue to increase in complexity, several design techniques have been proposed to improve circuit performance and maintain an acceptable design time. These are discussed hereafter.
FIG. 1A shows a pattern of an example of the conventional C MOS (complementary MOS) cell, and FIG. 1B shows an equivalent circuit of the C MOS cell of FIG. 1A and FIG. 1C is a detailed circuit connection diagram of the C MOS circuit. In FIG. 1A, the upper part p1 designates a p-channel transistor region and a lower part n1 designates an n-channel transistor region. A square region 1 encircled by a chain line is a unit cell. In FIG. 1A, numeral 2 designates aluminum wirings which are of an uppermost part, and which are mainly disposed in a first direction on a chip, which is vertical in FIG. 1. Numeral 3 designates wiring conductors formed with polycrystalline silicon or gate regions formed with the polycrystalline silicon films which are insulated from an underlying substrate with a lower insulation film, and insulated from the overlying aluminum wirings with an upper insulation film. Numerals 4, 6 and 7 designate impurity diffused regions which are source regions and drain regions. Numeral 5 designates interconnection parts between the aluminum wirings 2 and the underlying polycrystalline silicon conductors 3 which make connections through openings formed in the upper or lower insulation film and are schematically shown by a square with a cross therein. Fine dot marks on the aluminum wiring regions and broken line hatchings on the diffused regions are drawn for easier understanding of the configuration. The diffused regions 6, 6 of the p-channel transistor regions p1 and diffused regions 7,7 of the n-channel regions n1 are connected to power source potential and grounding potential, respectively.
The circuit of FIG. 1A forms, as shown in FIG. 1B, a four-input AND-OR composit gate circuit, which has a detailed circuit construction comprising four p-channel MOS transistors in the p-type regions p1 and four n-channel MOS transistors in the n-type regions n1, respectively, as shown in FIG. 1C. That is, as shown in FIG. 1A, the IC has p-channel MOS transistors in the upper p1 region and n-channel MOS transistors in the lower n1 region.
In such a conventional silicon gate MOS IC, since the diffused source regions and the diffused drain regions are formed by means of a self aligning process at both sides of each polycrystalline silicon gate electrode region, it is impossible to form lead-pit wiring made of polycrystalline silicon of the part other than the gate electrode parts in a manner to cross the diffused regions. That is, as shown in FIG. 1A, it is impossible to form conductors of polycrystalline silicon in the vertical direction of FIG. 1A between the regions p1 and n1, so as to cross the diffused regions 6 and 7 which are power source potential and ground potential lines respectively. If the polycrystalline silicon conductor is intended to be formed to cross the diffused regions, then the diffused region such as 6 or 7 is cut off under the part of the polycrystalline conductor, since the forming of the diffused region is made after forming the polycrystalline region. The present art of producing silicon gate MOS IC wiring is to form polycrystalline conductors on a semiconductor substrate with an insulation film inbetween and on the polycrystalline silicon conductors further aluminum wirings are formed with a second insulation film inbetween. Accordingly, the aluminum wiring can cross over the diffused region and the polycrystalline conductors. Accordingly, in the configuration of FIG. 1A wherein aluminum wirings A, B, C, D and O to connect function elements inside the cell are formed vertically as shown in FIG. 1A, it is impossible to form aluminum wirings so as to run horizontally of FIG. 1A between the cells in a p-type region or n-type region in line in the horizontal direction of FIG. 1A, since there are already vertical aluminum wirings between the horizontally neighboring cells. Accordingly, in the device of FIG. 1A, polycrystalline silicon must be used as wiring to lead out in a horizontal direction from the cells.
FIG. 2 shows a schematic view of an IC which is formed by combining a plural number of logic cells in a horizontal direction and in a vertical direction in accordance with a known building block construction. In FIG. 2 the blocks L.sub.1, L.sub.2 . . . L.sub.n, L.sub.m, L.sub.m+1 . . . L.sub.m+n show circuit construction and spatial construction of logic cells each composed as shown in FIG. 1A to FIG. 1B, and a plural number of cells in a horizontal direction L.sub.1, L.sub.2 . . . L.sub.n form a logic circuit block I. Another plural number of cells L.sub.m, L.sub.m+1 . . .L.sub.m+n form a next logic circuit block II. For instance, in a microcomputer or the like, a data bus line has a number of connections in a logic circuit block and control lines between the logic circuit blocks are formed to cross the bus line. As shown in the foregoing elucidation, in each logic circuit block, p-type MOS transistor region such as p1 and n-type MOS transistor region such as n1 are interconnected by aluminum wires l.sub.A1, and electrical interconnection of the logic circuit blocks I, II . . . are made by aluminum wirings l.sub.A2, to which polycrystalline silicon conductor wirings l.sub.S1, l.sub.S2 . . . are connected in a horizontal direction. For instance, an electrode in a cell L.sub.1 is led out horizontally by the polycrystalline silicon conductor wiring l.sub.S1 to the vertical aluminum wiring l.sub.A2, and an electrode in a cell L.sub.m+1 is led out by a horizontal polycrystalline silicon conductor wiring l.sub.S2 to the vertical aluminum wiring l.sub.A2 and the electrodes of the cells L.sub.1 and L.sub.m+1 are connected through the polycrystalline silicon conductors l.sub.S1, aluminum wiring l.sub.A2 and polycrystalline silicon wiring l.sub.S2. Mark l.sub.S3 in FIG. 2 shows a polycrystalline silicon conductor wiring and l.sub.A3 is another vertical aluminum wiring. Substantially vertical lines l.sub.AC show control lines which are aluminum wirings connecting the vertically disposed logic circuit cells.
As shown in FIG. 2, the conventional device uses aluminum vertical wirings and polycrystalline silicon horizontal wirings. Due to the considerable resistance of the long polycrystalline silicon wiring, the signal propagation time is not negligible and high speed operation cannot be expected. That is, in an actual logic IC of a microprocessor or the like for instance, the horizontal bus lines l.sub.S1, l.sub.S2, l.sub.S3 of polycrystalline silicon wirings become several tens .mu.m to 1 mm in total. When a high speed operation at several MHz or higher frequency is necessary, the high speed operation of the logic circuit becomes impossible.
Hitherto, when the integration scale of the IC is not so large, there has been no need of integrating the complementary circuit cells in vertical rows and in horizontal lines. In such conventional case of a relatively small IC, guard bands to surround periphery regions of the p-type MOS transistor region or n-type MOS transistor region are formed by means of an impurity diffusion process. When there is no particular need in stacking a plural number of logic circuit cells in the vertical direction, no particular problem takes place with cells like FIG. 1A.
However, in a large scale integrated circuit such as random logic represented by a microcomputer, there is a necessity of integrating a certain number of logic circuit blocks in 8 stages or 16 stages or the like of many stages, which must be mutually connected, and the above-mentioned problem arises.
FIG. 3 shows a detailed construction of the circuit configuration of the FIG. 2 circuit. Therein, in the logic circuit blocks I, II . . . , the n-type MOS transistor region n1 and an n-type MOS transistor region n2 are disposed in neighboring relationship and connection between the blocks I and II is made by aluminum wirings l.sub.A2, and other aluminum wirings l.sub.A3 and l.sub.A4 are connected to suitable diffused regions 6 and 7. As above-mentioned, when a very complicated logic circuit block construction is constituted by utilizing the configuration of the cell of FIG. 1, then it is necessary that the bus lines l.sub.S1, l.sub.S2, l.sub.S3 must be horizontally led out by polycrystalline silicon conductor wirings, and due to its poor signal transmission characteristic, a high speed operation is impossible. Even if aluminum wirings such as l.sub.A2 is used as a part of a bus line as shown in FIG. 2 and FIG. 3, as the distance of leading of the polycrystalline silicon conductor wirings l.sub.S1, l.sub.S2 becomes long, the advantage of using the aluminum wirings are not fully effected and high frequency operation is difficult. Generally, the aluminum wiring has a specific resistivity of about 20 m.OMEGA./.quadrature., while that of the polycrystalline silicon wirings is more than 10 .OMEGA./.quadrature. even when a high concentration impurity is doped, the conductivity of aluminum wirings is about several hundred times larger than that of the polycrystalline silicon wirings. This means that the signal transmission speed of the former is faster by several times than the latter.
FIG. 4 shows another example of a conventional logic circuit cell for increasing signal transmission speed by using aluminum wirings in a horizontal direction, taking account of the above-mentioned situation. In FIG. 4, the corresponding part to those of the above-mentioned conventional example shown in FIG. 1 through FIG. 3, are designated by the corresponding numerals and elucidations of them are omitted for simplicity. And power source potential and ground potential are given by aluminum wirings 6A and 7A to respective diffused regions.
FIG. 5 shows a configuration of an IC wherein a number of cells shown in FIG. 4 are used. In FIG. 4, cell L.sub.1m, L.sub.2m, L.sub.3m . . . together form a first logic block I and cell L.sub.3m+1, L.sub.3m+2 . . . form a second logic circuit block II. In the configuration of FIG. 4, the problem of the conventional example of FIG. 1 through FIG. 3 is improved, that is, signal propagation delay is improved by disposing the aluminum wirings for instance, shown in FIG. 5 as l.sub.A11, l.sub.A12, l.sub.A13 . . . in a horizontal direction; but in this case, vertical wiring of the aluminum wiring is not possible. In this configuration of FIG. 5, since no diffused regions to define the power source potential and ground potential are formed in the p-channel MOS transistor region and n-channel MOS transistor region, vertical connections inside the cells and towards outside the cells can be made by vertical polycrystalline silicon wirings l.sub.S11, l.sub.S12, l.sub.S13, l.sub.S14, . . . As abovementioned, the configuration shown by FIG. 4 and FIG. 5 enables forming interblock vertical connections by means of polycrystalline silicon wirings and intercell horizontal connections by means of horizontal aluminum wirings. Accordingly, the conventional problem of the configuration of FIG. 1 through FIG. 3 of difference in signal propagation speed is alleviated.
However, the configuration of FIG. 4 and FIG. 5 has the following two problems.
(1) Since the vertical wirings are formed with polycrystalline silicon wirings l.sub.S11, l.sub.S12, l.sub.S13 and l.sub.S14, when the number of vertical rows of the logic circuit blocks I, II, . . . increases, the polycrystalline silicon wiring in total becomes long, and delay of the signal propagation thereon can not be neglected. For instance, when the logic circuit blocks . . . I, II . . . becomes 8 stages, then the length of the polycrystalline silicon wirings becomes more than 1 mm and the signal propagation becomes very slow, damaging satisfactory operation.
(2) Because of existence of the polycrystalline silicon wirings in the vertical direction, horizontally extending diffused regions to define the power source potential and ground potential cannot be made thereunder. Accordingly, it is not possible to form guard band regions around a p-well region formed in the n-type semiconductor substrate, therefore it is likely to produce latching-up.